IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates
-
- HASHIZUME Masaki
- Faculty of Engineering, The University of Tokushima
-
- TAKEDA Teppei
- Faculty of Engineering, The University of Tokushima
-
- ICHIMIYA Masahiro
- Faculty of Engineering, The University of Tokushima
-
- YOTSUYANAGI Hiroyuki
- Faculty of Engineering, The University of Tokushima
-
- MIURA Yukiya
- Graduate School of Engineering, Tokyo Metropolitan University
-
- KINOSHITA Kozo
- Faculty of Informatics, Osaka Gakuin University
この論文をさがす
抄録
In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I_<DDQ> sensor design and external I_<DDQ> sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.
収録刊行物
-
- IEICE transactions on information and systems
-
IEICE transactions on information and systems 85 (10), 1534-1541, 2002-10-01
一般社団法人電子情報通信学会
- Tweet
詳細情報 詳細情報について
-
- CRID
- 1570854177260582912
-
- NII論文ID
- 110006376583
-
- NII書誌ID
- AA10826272
-
- ISSN
- 09168532
-
- 本文言語コード
- en
-
- データソース種別
-
- CiNii Articles