A 350-MS/s 3.3-V 8-bit CMOS D/A Converter Using a Delayed Driving Scheme

2 Citations 5 References

Bibliographic Information

Other Title
  • 遅延駆動手法を用いた 350MS/s 3.3V 8bit CMOS D/A コンバｰタ

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Description

This paper describes a 350-MS/s 8-bit CMOS D/A converter with 3. 3-V power supply. A current source with a driving scheme is developed. This driving scheme reduces fluctuation of internal node voltage of the source and high-speed switching is realized. Two stages of latches are inserted into matrix decoder for reducing glitch energy and for enhancing decoding speed. The D/A converter is fabricated in a 0.5-μm CMOS process. Its settling time is less than 2.4 ns and it successfully operates at 350 MS/s.

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Details 詳細情報について

  • CRID
    1570854177377178240
  • NII Article ID
    110003198162
  • NII Book ID
    AN10013094
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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