A Cache memory Control Mechanism for On-chip Multiprocessors

6 References

Bibliographic Information

Other Title
  • オンチップマルチプロセッサのキャッシュメモリ制御方式

Search this article

Description

A new cache coherence solution is proposed for an over 500MHz on-chip multiprocessor using advanced VLSI technology. In order to reduce shared-bus transaction time, the central coherence unit (CCU) is introduced. The CCU controls all shared-bus transactions, monitoring all cache tags every clock cycle. A new cache coherence protocol is also introduced in order to reduce external memory access. An implementation of CCU and CRAC is presented and evaluated using a cycle-based multiprocessor simulator.

Journal

  • Technical report of IEICE. ICD

    Technical report of IEICE. ICD 96 (20), 81-88, 1996-04-25

    The Institute of Electronics, Information and Communication Engineers

References(6)*help

See more

Keywords

Details 詳細情報について

  • CRID
    1570854177460403584
  • NII Article ID
    110003316797
  • NII Book ID
    AN10013276
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

Report a problem

Back to top