Testable Static CMOS PLA for IDDQ Testing
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- HASHIZUME Masaki
- Faculty of Engineering, University of Tokushima
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- HOSHIKA Hiroshi
- Faculty of Engineering, University of Tokushima
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- YOTSUYANAGI Hiroyuki
- Faculty of Engineering, University of Tokushima
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- TAMESADA Takeomi
- Faculty of Engineering, University of Tokushima
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抄録
A new IDDQ tastable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of NOR-NOR type is designed using this method. It is shown that all bridging faults in NOR planes of the tastable designed PLA circuit can be detected by IDDQ testing with 4 sets of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed using this method so that the quiescent supply current generated when they are tested will be zero. Thus, high resolution of IDDQ tests for the PLA circuits can be obtained by using the testable design method. Results of IDDQ tests of PLA circuits designed using this testable design method confirm not that the expected output can be generated from the circuits but that the circuits are fabricated without bridging faults in NOR planes. Since bridging faults often occur in state-of-the-art IC fabrication, the testable design is indispensable for realizing highly reliable logic systems.
収録刊行物
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- IEICE transactions on fundamentals of electronics, communications and computer sciences
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IEICE transactions on fundamentals of electronics, communications and computer sciences 84 (6), 1488-1495, 2001-06-01
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詳細情報 詳細情報について
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- CRID
- 1571135652357071360
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- NII論文ID
- 110003208959
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- NII書誌ID
- AA10826239
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- ISSN
- 09168508
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles