A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits
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- HIGUCHI Hisayuki
- the Cental Research Laboratory, Hitachi, Ltd.
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- TACHIBANA Suguru
- the Cental Research Laboratory, Hitachi, Ltd.
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- MINAMI Masataka
- Semiconductor Division, Hitachi Ltd.
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- NAGANO Takahiro
- Semiconductor Division, Hitachi Ltd.
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説明
Low-power, high-speed match-detection circuits for a content addressable memory (CAM) are proposed and evaluated. The circuits consist a current supply to a match-line, a differential amplifier, and 9-MOSFET CAM cells. The implementation of these circuits made it possible to realize a 16-entry, 32-bit data-compare CAM TEG of 1.2-ns match-detection time with 5-mW power dissipation in 10-ns cycle-time.
収録刊行物
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- IEICE transactions on electronics
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IEICE transactions on electronics 79 (6), 757-762, 1996-06-25
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詳細情報 詳細情報について
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- CRID
- 1571417127440972800
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- NII論文ID
- 110003211084
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- NII書誌ID
- AA10826283
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- ISSN
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles
