An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)
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- ENDOH Tetsuo
- Research Institute of Electrical Communication, Tohoku University
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- NAKAMURA Tairiku
- Research Institute of Electrical Communication, Tohoku University
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- MASUOKA Fujio
- Research Institute of Electrical Communication, Tohoku University
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説明
A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.957% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.
収録刊行物
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- IEICE transactions on electronics
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IEICE transactions on electronics 80 (7), 911-917, 1997-07-25
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詳細情報 詳細情報について
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- CRID
- 1571698602418095616
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- NII論文ID
- 110003211289
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- NII書誌ID
- AA10826283
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- ISSN
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles
