An Analog Circuit Forming Topological Mapping and Its Learning Algorithm

8 References
  • SUDO Daisaku
    Department of Electrical and Electronic Engineering, Toyohashi University of Technology
  • TSUJI Kiyotaka
    Department of Electrical and Electronic Engineering, Toyohashi University of Technology
  • IO Eiji
    Department of Electrical and Electronic Engineering, Toyohashi University of Technology
  • IKEDA Hitoshi
    Department of Electrical and Electronic Engineering, Toyohashi University of Technology
  • OHSHIMA Naoki
    Department of Electrical and Electronic Engineering, Toyohashi University of Technology
  • SHIN Jang-Kyoo
    Department of Electrical and Electronic Engineering, Toyohashi University of Technology
  • YONEZU Hiroo
    Department of Electrical and Electronic Engineering, Toyohashi University of Technology

Bibliographic Information

Other Title
  • トポロジカルマッピング形成を行う電子回路の学習アルゴリズムと回路構成

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Description

It is known mathematically that the topological mapping can be formed by Winner-Take-All (WTA) mechanism. Since variations of device characteristics certainly exist, the topological mapping can't be formed through learning in analog circuits based on a mathematical WTA algorithm. We proposed a new algorithm and a new network model for hardware implementation to form me topological mapping. As a result, it appeared that the analog circuit can form the topological mapping with a high probability.

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Details 詳細情報について

  • CRID
    1571980077399673600
  • NII Article ID
    110003233072
  • NII Book ID
    AN10091178
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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