A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM

NAMBU Hiroaki, KANETANI Kazuo, IDEI Youji, MASUDA Toru, HIGETA Keiichi, OHAYASHI Masayuki, USAMI Masami, YAMAGUCHI Kunihiko, KIKUCHI Toshiyuki, IKEDA Takahide, OHHATA Kenichi, KUSUNOKI Takeshi, HOMMA Noriyuki

A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM

参考文献34件

NAMBU Hiroaki

the Advanced Devices Research Department, Central Research Laboratory, Hitachi, Ltd.
KANETANI Kazuo

the Advanced Devices Research Department, Central Research Laboratory, Hitachi, Ltd.
IDEI Youji

the Advanced Devices Research Department, Central Research Laboratory, Hitachi, Ltd.
MASUDA Toru

the Advanced Devices Research Department, Central Research Laboratory, Hitachi, Ltd.
HIGETA Keiichi

the Device Development Center, Hitachi, Ltd.
OHAYASHI Masayuki

the Device Development Center, Hitachi, Ltd.
USAMI Masami

the Device Development Center, Hitachi, Ltd.
YAMAGUCHI Kunihiko

the Device Development Center, Hitachi, Ltd.
KIKUCHI Toshiyuki

the Device Development Center, Hitachi, Ltd.
IKEDA Takahide

the Device Development Center, Hitachi, Ltd.
OHHATA Kenichi

Hitachi Device Engineering, Ltd.
KUSUNOKI Takeshi

Hitachi Device Engineering, Ltd.
HOMMA Noriyuki

Hosei University

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説明

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm^2 memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers.