A Simple Evaluation Formula for Parallel Plate Mode Suppression by Via-hole Partition
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- YUASA Takeshi
- Information Technology R&D Center MITSUBISHI ELECTRIC CORPORATION
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- NISHINO Tamotsu
- Information Technology R&D Center MITSUBISHI ELECTRIC CORPORATION
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- OH-HASHI Hideyuki
- Information Technology R&D Center MITSUBISHI ELECTRIC CORPORATION
Bibliographic Information
- Other Title
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- VIAホール列による平行平板モード抑圧量の簡易評価式
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Description
Couplings by a parallel plate mode between terminals in a multi-layered RF package are a common problem that degrades circuit performance. Via-holes that short-circuit ground planes are used for suppressing this mode. Quantitative evaluation of relations between the amount of suppression and various parameters, such as the number of column, diameters and pitches of via-holes is required for optimal disposition of the via-holes. In this paper, a simple evaluation formula that describes the amount of the suppression is derived by mode-matching technique. The results of comparison with the finite element method validate our proposing formula.
Journal
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- IEICE technical report. Electron devices
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IEICE technical report. Electron devices 102 (557), 57-60, 2003-01-10
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1573105977259327232
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- NII Article ID
- 110003175275
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- NII Book ID
- AN10012954
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- Text Lang
- ja
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- Data Source
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- CiNii Articles