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Feasibility of Si Resonant Tunneling MOS Transistor (SRT-MOST) to New Multi-Valued Logic Circuit
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- MATSUO Naoto
- Department of Material Science, Himeji Institute of Technology
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- YAMAMOTO Akinori
- Department of Electronic & Electric Engineering, Yamaguchi University
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- KITAMON Yoshitaka
- Department of Electronic & Electric Engineering, Yamaguchi University
Bibliographic Information
- Other Title
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- Si 共鳴トンネリング MOS トランジスタによる多値論理回路の可能性
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Description
シリコン共鳴トンネリングMOSトランジスタ(SRTMOST)による論理回路により,多値論理回路の可能性を検討した.CMOSのインバータ回路におけるN-MOSFETを二つのN-SRTOMOSの並列回路に置き換えた.出カ特性は高電位低電位のほかに二つのプラトーな領域が現れた.この結果はSRTMOSTを使った論理回路により,多値論理回路を実現できることを示すものである.
Journal
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- The transactions of the Institute of Electronics, Information and Communication Engineers. C
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The transactions of the Institute of Electronics, Information and Communication Engineers. C 86 (12), 1370-1371, 2003-12-01
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1573105977259644544
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- NII Article ID
- 110003172101
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- NII Book ID
- AA11412446
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- ISSN
- 13452827
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- Text Lang
- ja
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- Data Source
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- CiNii Articles