A New Method for Calculating One-dimensional Process Margin in Consideration of Process Variation

1 References
  • MIWA Tadashi
    Semiconductor Manufacturing Engineering Center, Toshiba Corporation
  • NODA Tomonobu
    Semiconductor Manufacturing Engineering Center, Toshiba Corporation
  • AKIYAMA Tatuo
    Semiconductor Manufacturing Engineering Center, Toshiba Corporation
  • SUGIMOTO Shigeki
    Semiconductor Manufacturing Engineering Center, Toshiba Corporation

Bibliographic Information

Other Title
  • プロセスばらつきを考慮した一次元プロセスマージン計算法の開発

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Description

The yield and device characteristics in LSI have become more sensitive to their process variation, as the design rule is more shrinked and larger wafer is used. So the process variation such as between and within wafers should be taken account in process integration to eliminate yield loss. But actually it's difficult to make experiment which can cover possible variations all in process because of cost and time. That's why some calculation method have been required recently. In this paper, we report a new method for calculating one-dimensional(vertical direction such as etching and deposition)process margin in consideration of process variation using Monte Carlo simulation.

Journal

  • Technical report of IEICE. SDM

    Technical report of IEICE. SDM 98 (349), 9-16, 1998-10-22

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1573105977274886528
  • NII Article ID
    110003310115
  • NII Book ID
    AN10013254
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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