Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field
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- YOTSUYANAGI Hiroyuki
- Faculty of Engineering, University of Tokushima
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- IWAKIRI Taisuke
- Faculty of Engineering, University of Tokushima
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- HASHIZUME Masaki
- Faculty of Engineering, University of Tokushima
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- TAMESADA Takeomi
- Faculty of Engineering, University of Tokushima
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抄録
In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.
収録刊行物
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- IEICE transactions on information and systems
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IEICE transactions on information and systems 86 (12), 2666-2673, 2003-12-01
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詳細情報 詳細情報について
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- CRID
- 1573668927254908928
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- NII論文ID
- 110003213691
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- NII書誌ID
- AA10826272
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- ISSN
- 09168532
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles