User Program Controlled Hierarchical Memory System

MAKI Nobuhiro, OKAMOTO Shusuke, SOWA Masahiro

Execution ability of processors has been getting higher and higher. As a result, it needs memories which is big size and can access within slight time. It is difficult to realize in its construction and its principle. So recently cache memory system is used. But, cache miss sometimes occurs in cache memory system. If cache miss occurs frecuently, it spoils the processor's abilty. One of the reasons why cache miss occurs frecuently is to replace the contains between cache memory and main memory by constant algorithm. Therefore the programmer who knows the data movement in the programs programs not only application program but also specified programs which replace the contains. That had better lead the slightest cache misses latency. In this paper, we propose the new memory system and argue the solution of the problem which the system have potentially. And then we show the simple performance review of this system. The result shows that this system can reduce the cache miss latency extremely.

User Program Controlled Hierarchical Memory System

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