A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits

TACHIBANA Suguru, HIGUCHI Hisayuki, TAKASUGI Koichi, SASAKI Katsuro, YAMANAKA Toshiaki, NAKAGOME Yoshinobu

A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits

参考文献6件

TACHIBANA Suguru

the ULSI Research Center, Central Research Laboratory, Hitachi, Ltd.
HIGUCHI Hisayuki

the ULSI Research Center, Central Research Laboratory, Hitachi, Ltd.
TAKASUGI Koichi

the ULSI Research Center, Central Research Laboratory, Hitachi, Ltd.
SASAKI Katsuro

the ULSI Research Center, Central Research Laboratory, Hitachi, Ltd.
YAMANAKA Toshiaki

the ULSI Research Center, Central Research Laboratory, Hitachi, Ltd.
NAKAGOME Yoshinobu

the ULSI Research Center, Central Research Laboratory, Hitachi, Ltd.

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説明

The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM, and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-μm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6ns.