A FinFET design based on three-dimensional process and device simulations
説明
In this paper, a practical design method of a FinFET is presented with :in example of a scaled DRAM device. The electric properties of the FinFET are analyzed by means of three-dimensional process and device simulations. The analysis reveals that the short channel effects depend strongly on not only the thickness but also the taper angle of the silicon pillar. The device is optimized successfully assuming the tapered shape for the silicon pillar. The simulated characteristics (0.1fA off-leak current and 62/spl mu/A drive current per unit cell @ 85C) well agree with experimental results.
収録刊行物
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- International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.
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International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. 179-182, 2003-01-01
IEEE
