Parallel nonvolatile programming of power-up states of SRAM cells
説明
In this paper, we propose a parallel programmable non-volatile memory using an ordinary static random access memory (SRAM). Parallel non-volatile programming of the power-up states of the entire SRAM array is achieved by simply applying high-voltage stress to the power supply terminal after storing inverted desired data in the SRAM array. Successful 2kbit non-volatile programming and recalling of the power-up states are demonstrated using a device-matrix-array (DMA) test element group (TEG) fabricated by 0.18 μm technology.
収録刊行物
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- 2017 IEEE 12th International Conference on ASIC (ASICON)
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2017 IEEE 12th International Conference on ASIC (ASICON) 418-421, 2017-10-01
IEEE
