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80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process
Description
Double offset-implanted source/drain extension and 550/spl deg/C silicon nitride deposition for sidewall and borderless contact have been applied to sub-0.1 /spl mu/m CMOS for improvement of short channel effect as well as parasitic resistance. Consequently, 830/400 /spl mu/A//spl mu/m drive current with 2.5 nm gate insulator has been achieved under 1 nA//spl mu/m off-leakage at 1.5 V operation with short channel tolerance to 80 nm gate length.
Journal
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- International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)
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International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) 239-242, 2002-11-11
IEEE
