Gate matrix multiple-folding algorithm (for CMOS VLSI)
説明
The authors propose a new multiple-folding algorithm for the gate matrix layout. It was applied to generation of rectangular blocks with a flexible size. The algorithm consists of two phases, net partitioning and the gate arrangement, and both are based on the generalized minicut technique. In the first and second phases, the width and height of the multiple-folded gate matrix block are directly minimized, respectively, such that the area is minimized and the desired aspect ratio of the block is obtained. The experimental results showed the effectiveness of the algorithm. >
収録刊行物
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- [Proceedings] 1992 IEEE International Symposium on Circuits and Systems
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[Proceedings] 1992 IEEE International Symposium on Circuits and Systems 4 2001-2004, 2003-01-02
IEEE
