An extended class of sequential circuits with combinational test generation complexity
説明
We introduce a class of sequential circuits with internally switched balanced structure which allows test generation with combinational test generation complexity. The proposed class includes any other known classes with this feature. This paper also considers faults in hold registers and switches regarded as macros, while any related work does not consider faults in such macros. Experimental results show the effectiveness of using combinational test generation for the circuits with internally switched balanced structure.
収録刊行物
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- Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors
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Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors 200-205, 2003-06-26
IEEE Comput. Soc
