Physics of interfaces between gate electrodes and high-k dielectrics

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Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, the authors have found that the work-function pinning-free-region generally appears due to the difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. Further, the authors also discuss the interface physics between pure metal gates and high-k dielectrics

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