Synergistic power/area optimization with transistor sizing and wire length minimization [CMOS logic]
説明
The paper proposes a method to realize low-power control-logic modules by combining transistor-size optimization and transistor layout. When applied to a circuit with 10,000 transistors, the optimizer has reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.
収録刊行物
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- Proceedings of 1994 IEEE Symposium on Low Power Electronics
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Proceedings of 1994 IEEE Symposium on Low Power Electronics 50-51, 2002-12-17
IEEE