A stacked DCFL structure applied to a prescalar IC and investigated for ASICs
説明
The stacked DCFL (direct coupled FET logic) structure makes it possible to have supply voltage compatibility to Si LSIs with IC circuit current reduction. The idea is to stack DCFL circuits by utilizing the Schottky FET characteristic, which makes the total DCFL circuit current hold constantly independent of any logic conditions. This circuit structure was applied to the divide by 64/65 or 128/129 prescalar IC, which operates at 2.5 GHz on a supply voltage of 3 V with circuit current of 9.8 mA. Virtual ground stability was investigated to apply the stacked DCFL to application-specific integrated circuits (ASICs). The stability of the virtual ground was confirmed by modeling the stacked DCFL circuit and simulating the circuit using SPICE. >
収録刊行物
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- GaAs IC Symposium Technical Digest 1992
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GaAs IC Symposium Technical Digest 1992 109-112, 2003-01-02
IEEE
