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Low power design and its testability
Description
In this paper, we propose a power reduction tool named PORT, which evaluates the power dissipation factor /spl Phi/ by utilizing the transition probability, and which reduces /spl Phi/ by utilizing sets of permissible functions. Experimental results show the usefulness of PORT. Next, we will consider on the testability of circuits transformed by PORT. The size of the test set generated by compact test set generator, the number of redundant faults and the number of paths are used as testability parameters for detecting stuck-at and delay faults. Experimental results show that the test size of the circuit transformed by PORT is smaller than or equal to that of original one, but transformations by PORT increase the number of paths.
Journal
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- Proceedings of the Fourth Asian Test Symposium
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Proceedings of the Fourth Asian Test Symposium 361-366, 2002-11-19
IEEE Comput. Soc. Press
