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Pipelined design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers
Description
In this paper, a high-speed RSA encryption processor employing a highly parallel architecture based on the redundant binary number arithmetic, table-look-up, and pipelining is presented. It is demonstrated that the encryption time of the presented processor is about 1/12 that of conventional processors and that the encryption rate for continuous input data is about 3/2 that of conventional processors.
Journal
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- 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings.
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2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings. 412-415, 2004-03-01
IEEE