DFT techniques for wafer-level at-speed testing of high-speed SRAMs

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Description

Design-for-test (DFT) techniques for acquiring at-speed function fail bit maps with conventional wafer test equipment are proposed. The SRAM core is operated with a high frequency clock generated by a gain-suppressed VCO which can reduce clock jitter. The data are output with a data out strobe control circuit synchronizing with an external low frequency clock. Using these techniques, the SRAM chip appears to be operating with a low frequency tester clock while the SRAM core is operated with a high frequency internal clock. Therefore, a fail bit map at high frequency operation can be obtained with conventional wafer test equipment. The at-speed test with fail bit map acquisition allows slow bit cell replacement to spare cell or chip-by-chip internal timing optimization with fuse-blowing. It results in a drastic reduction in test cost and performance yield improvement.

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