Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor

DOI PDF 被引用文献11件
  • Anne S. Verhulst
    IMEC 1 , Kapeldreef 75, 3001 Leuven, Belgium
  • Bart Sorée
    K.U.Leuven 2 Department of Electrical Engineering, , Kasteelpark Arenberg 10, 3001 Leuven, Belgium
  • Daniele Leonelli
    K.U.Leuven 2 Department of Electrical Engineering, , Kasteelpark Arenberg 10, 3001 Leuven, Belgium
  • William G. Vandenberghe
    K.U.Leuven 2 Department of Electrical Engineering, , Kasteelpark Arenberg 10, 3001 Leuven, Belgium
  • Guido Groeseneken
    K.U.Leuven 2 Department of Electrical Engineering, , Kasteelpark Arenberg 10, 3001 Leuven, Belgium

書誌事項

公開日
2010-01-15
DOI
  • 10.1063/1.3277044
公開者
AIP Publishing

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説明

<jats:p>Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.</jats:p>

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