The impact of wafer edge profile on polishing performance in silicon wafer manufacturing

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  • シリコンウェーハ製造研磨におけるウェーハエッジ形状の影響評価
  • シリコン ウェーハ セイゾウ ケンマ ニ オケル ウェーハ エッジ ケイジョウ ノ エイキョウ ヒョウカ

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Reducing edge roll-off of silicon wafers is becoming increasingly important for uniform treatment near the wafer edge in both lithographic and CMP processes of semiconductor manufacture. Optimization of the wafer edge profile in terms of CMP uniformity during silicon wafer manufacturing is proposed as one method to reduce edge roll-off. FEM analysis is used to calculate the contact pressure on the wafer surface, and the removal rate is estimated based on the calculated contact pressure that is proportional to the removal rate in polishing of silicon wafers. As a result, reduction of the edge roll-off would be achieved by shortening the edge width of the wafer in the case of both double-sided and single-sided polishing. This conclusion does not depend on the Young's modulus of the polishing pad over the range of Young's modulus of 1-15 MPa, and does not depend on carrier thickness in double-sided polishing when the carrier thickness does not exceed the wafer thickness.

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