A method of generating tests for redundant faults in combinational circuits by using delay effects

  • Yu Xiangqiu
    Depertment of Computer Science,Faculty of Engineering,Ehime University
  • Takahashi Hiroshi
    Depertment of Computer Science,Faculty of Engineering,Ehime University
  • Takamatsu Yuzo
    Depertment of Computer Science,Faculty of Engineering,Ehime University

Bibliographic Information

Other Title
  • 遅延効果を用いた組合せ回路における冗長故障のテスト生成法

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Description

Practical combinational circuits include some undetectable stuck- at faults called the redundant faults.The redundand fault does not affect the functional behavior of the circuit even if it exists. The redundant fault,however,causes undesirable effects to the circuit such as increase of delay time and decease of testability of the circuit.In this paper,we study the testing problem of the redundant fault in the combinational circuit by using delay effects and propose a method for generating a test-pair which can detect a redundant fault.By using an extended seven-valued calculus,the presented method generates a dynamically sensitizable path which includes a target redundant fault on a testricted single path,The dynamically sensitizable path can propagate the effect of the target redundant fault to the output of the circuit by delay effects. By the preliminary experiment on benchmark circuits,it is shown that test-pairs for some redundant faults can be generated theoretically.

Journal

  • Technical report of IEICE. FTS

    Technical report of IEICE. FTS 94 (128), 53-60, 1994-06-28

    The Institute of Electronics, Information and Communication Engineers

Details 詳細情報について

  • CRID
    1572543027237801728
  • NII Article ID
    110003194252
  • NII Book ID
    AN10012998
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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